Intern - Design Verification Infrastructure Engineer - Platform

SiFive

Hours: Full time
Where: Santa Clara, California, United States
Posted: Sep 2

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer.

What you'd do

Architect, develop, and maintain the Verification Platform to provide a common infrastructure that scales with the growth of SiFive for Design Verification and other verification and validation activities
Develop new functionality in Chisel and CIRCT to support Verification Platform libraries and tools
Develop Verification Platform libraries for expressing verification intent in Scala with Chisel, including test harnesses, stimulus, scoreboards, and other generators
Develop Verification Platform libraries for querying design intent in Python from verification tools, including from specs, generated metadata, and other sources
Develop Verification Platform tools and methodologies to support end-to-end flows used by Design Verification other verification and validation teams
Educate the Design Verification and other verification and validation teams on best practices and how to achieve them with the Verification Platform

What they want

Software engineering experience in at least one compiled language and one scripting language
Understanding of modern software engineering practices
Experience deploying software systems into production environments
Experience with Chisel, CIRCT, and/or MLIR
History working on systems software like compilers, databases, and/or operating systems
Understanding of EDA tools and flows for Design Verification

Starts: 2026-08-01