The board
- Hours
- Full time
- Where
- Santa Clara, CA
- Posted
- Sep 17
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The Compute and Custom Solutions (CCS) Business Unit within Marvell develops cutting-edge SoCs and processors in advanced process nodes for some of the largest companies in the world.
What you'd do
- Develop understanding of the block level or chip top DFT and pattern generation flows for complex SOC designs
- Execute DFT insertion, pattern generation and verification flows for Scan, Memory Built-in Self-Test (MBIST), Boundary Scan and IP macro test
- Run DFT checks and analyze results to resolve testability issues and improve DFT coverage
- Support DFT flow automation through scripting (Tcl, Python, or shell) to improve design flows
- Contribute to DFT documentation, methodology improvements and automation
- Present intern project results to the team at the end of the internship
What they want
- Currently pursuing a Masters in Computer Engineering, Electrical Engineering, or related fields
- Good understanding of digital logic design using Verilog/System Verilog
- Knowledge of DFT concepts, JTAG standards and Boundary scan implementation
- Knowledge of Scan test, memory BIST/BISR, functional test, JTAG, and other test methodologies is a plus
- Experience in programming and scripting languages such as Python, Shell, Tcl
- Knowledge of using AI assisted tools for coding, scripts and automation is a plus
- Effective teamwork and communication skills
- Starts
- 2026-09-17